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CAT522
Configured Digitally Programmable Potentiometer (DPPTM): Programmable Voltage Applications
FEATURES Two 8-bit DPPs configured as programmable voltage sources in DAC-like applications Independent reference inputs Non-volatile NVRAM memory wiper storage Output voltage range includes both supply rails 2 independently addressable buffered output wipers 1 LSB accuracy, high resolution Serial Microwire-like interface Single supply operation: 2.7V - 5.5V Setting read-back without effecting outputs
DESCRIPTION
The CAT522 is a dual, 8-bit digitally-programmable potentiometer (DPPTM) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for selfcalibrating systems and for applications where equipment which requires periodic adjustment is either difficult to access or in a hazardous environment. The CAT522 offers two independently programmable DPPs each having its own reference inputs and each capable of rail to rail output swing. The wipers are buffered by rail to rail opamps. Wiper settings, stored in non-volatile NVRAM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can be dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the DPP's output. The CAT522 is controlled with a simple 3-wire, microwire-like serial interface. A Chip Select pin allows several devices to share a common serial interface. Communication back to the host controller is via a single serial data line thanks to the CAT522 Tri Stated Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of the non-volatile NVRAM memory Erase/Write cycle. The CAT522 is available in the 0C to 70C commercial and -40C to 85C industrial operating temperature ranges. Both 14-pin plastic DIP and surface mount packages are available.
For Ordering Information details, see page 14.
APPLICATIONS Automated product calibration. Remote control adjustment of equipment Offset, gain and zero adjustments in selfcalibrating and adaptive control systems. Tamper-proof calibrations. DAC (with memory) substitute.
PIN CONFIGURATION PDIP 14-Lead (L) SOIC 14-Lead (W)
VDD CLK RDY/ BSY CS DI DO PROG 1 2 3 14 13 12 VREFH1 VREFH1 VOUT1 VOUT2 VREFL2 VREFL1 GND
4 CAT522 11 5 6 7 10 8 8
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. MD-2004 Rev. F
CAT522
FUNCTIONAL DIAGRAM
VDD 1 RDY/BSY 3 VREFH1 VREFH2 14 13
PROG
7
PROGRAM CONTROL
WIPER CONTROL REGISTERS AND NVRAM
24k
+ -
11
VOUT2
DI CLK CS
5 2 4 SERIAL CONTROL
24k
+ -
12
VOUT1
SERIAL DATA OUTPUT REGISTER
6
DO
CAT522
8 GND 9 10
VREFL1 VREFL2
Doc. No. MD-2004 Rev. F
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CAT522
ABSOLUTE MAXIMUM RATINGS (1) Parameters Supply Voltage VDD to GND Inputs CLK to GND CS to GND DI to GND RDY/BSY to GND PROG to GND VREFH to GND VREFL to GND Ratings -0.5 to +7 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 Units V Parameters Outputs D0 to GND VOUT 1- 4 to GND Operating Ambient Temperature Commercial (`C' or Blank suffix) Industrial (`I' suffix) Junction Temperature Storage Temperature Lead Soldering (10s max) Ratings -0.5 to VDD +0.5 -0.5 to VDD +0.5 0 to +70 -40 to +85 +150 -65 to +150 +300 Units V V C C C C C
V V V V V V V
RELIABILITY CHARACTERISTICS Symbol VZAP(2) ILTH(2) (3) Parameter ESD Susceptibility Latch-Up Test Method MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 2000 100 Max Units V mA
POWER SUPPLY Symbol IDD1 IDD2 VDD Parameter Supply Current (Read) Supply Current (Write) Operating Voltage Range Conditions Normal Operating Programming, VDD = 5V VDD = 3V Min -- -- -- 2.7 Typ 400 1600 1000 -- Max 600 2500 1600 5.5 Units A A A V
LOGIC INPUTS Symbol IIH IIL VIH VIL Parameter Input Leakage Current Input Leakage Current High Level Input Voltage Low Level Input Voltage Conditions VIN = VDD VIN = 0V Min -- -- 2 0 Typ -- -- -- -- Max 10 -10 VDD 0.8 Units A A V V
LOGIC OUTPUTS Symbol VOH VIL Parameter High Level Output Voltage Low Level Output Voltage Conditions IOH = -40A IOL = 1mA, VDD = +5V IOL = 0.4mA, VDD = +3V Min VDD -0.3 -- -- Typ -- -- -- Max -- 0.4 0.4 Units V V V
Notes: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V.
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. MD-2004 Rev. F
CAT522
POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol RPOT Parameter Potentiometer Resistance RPOT to RPOT Match Pot Resistance Tolerance Voltage on VREFH pin Voltage on VREFL pin Resolution INL DNL ROUT IOUT TCRPOT CH/CL Integral Linearity Error Differential Linearity Error Buffer Output Resistance Buffer Output Current TC of Pot Resistance Potentiometer Capacitances 300 8/8 2.7 0 0.4 0.5 0.25 1 0.5 10 3 -- Conditions Min Typ 24 0.5 1 20 VDD VDD - 2.7 Max Units k % % V V % LSB LSB mA ppm/C pF
AC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Digital tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tLZ tBUSY tPS tPROG tCLKH tCLKL fC Analog tDS DPP Settling Time to 1 LSB CLOAD = 10pF, VDD = +5V CLOAD = 10pF, VDD = +3V
Notes: (1) All timing measurements are defined at the point of signal crossing VDD / 2. (2) These parameters are periodically sampled and are not 100% tested.
Parameter Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Cycle Time PROG Setup Time Minimum Pulse Width Minimum CLK High Time Minimum CLK Low Time Clock Frequency
Conditions
Min 150 100 0 50
Typ -- -- -- -- -- -- -- 400 400 4 -- -- -- -- -- 3 6
Max -- -- -- -- -- 150 150 -- -- 5 -- -- -- -- 1 10 10
Units ns ns ns ns ns ns ns ns ns ms ns ns ns ns MHz s s
CL = 100pF
(1)
50 -- -- -- -- -- 150 700 500 300 DC -- --
Doc. No. MD-2004 Rev. F
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CAT522
A.C. TIMING DIAGRAM
to
1
2
3
4
5
tCLK H CLK
tCSS CS
tCLK L
t CSH
tCSMIN
tDIS DI tDIH
tLZ DO
t DO0
tHZ tDO1
PROG t PS tPROG RDY/BSY tBUSY
to
1
2
3
4
5
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Doc. No. MD-2004 Rev. F
CAT522
PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name VDD CLK RDY/BSY CS DI DO PROG GND VREFL1 VREFL2 VOUT2 VOUT1 VREFH2 VREFH1 Function Power supply positive Clock input pin Ready/Busy output Chip select Serial data input pin Serial data output pin EEPROM Programming Enable Input Power supply ground Minimum DPP1 output voltage Minimum DPP2 output voltage DPP2 output DPP1 output Maximum DPP2 output voltage Maximum DPP1 output voltage DPP addressing is as follows: DPP OUTPUT VOUT1 VOUT2 A0 0 1 A1 1 1
DEVICE OPERATION The CAT522 is a dual 8-bit configured digitally programmable potentiometer (DPP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPPs return to the settings stored in non-volatile memory. Each DPP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. DIGITAL INTERFACE The CAT522 employs a 3 wire serial, Microwire-like control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic "1" as a start bit. The DPP address and data are clocked into the DI pin on the clock's rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit.
Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. CHIP SELECT Chip Select (CS) enables and disables the CAT522's read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP control regis- ters will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in non-volatile memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been desensitized with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT522's clock controls both data flow in and out of the IC and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock's rising edge. While it is not neces- sary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being
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Doc. No. MD-2004 Rev. F
CAT522
saved may already be resident in the DPP wiper control register. No clock is necessary upon system power-up. The CAT522's internal power-on reset circuitry loads data from non-volatile memory to the DPPs without using the external clock. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. VREF VREF, the voltage applied between pins VREFH & VREFL, sets the DPP's Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH & VREFL are connected across the power supply rails. When using less than the full supply voltage be mindfull of the limits placed on VREFH and VREFL as specified in the References section of DC Electrical Characteristics. READY/BUSY When saving data to non-volatile memory, the Ready/Busy ouput (RDY/BSY ) signals the start and duration of the erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/BSY goes low and remains low until the programming cycle is complete. During this time the CAT521 will ignore any data appearing at DI and no data will be output on DO. RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the Figure 1. Writing to Memory
to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
minimum value required for non-volatile programming, RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. DATA OUTPUT Data is output serially by the CAT522, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 522s to share a single serial data line and simplifies interfacing multiple 522s to a microprocessor. WRITING TO MEMORY Programming the CAT522's non-volatile memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DPP address and eight data bits are clocked into the DPP wiper control register via the DI pin. Data enters on the clock's rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. Programming is accomplished by bringing PROG high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DPP wiper control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of generating and ramping up the programming voltage for data transfer to the non-volatile cells. The CAT522's non-volatile memory cells will endure over 1,000,000 write cycles and will retain data for a minimum of 100 years without being refreshed.
CS NEW DPP DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 D6 D7
PROG
RDY/BSY
DPP OUTPUT
CURRENT DPP VALUE NON-VOL ATILE
NEW DPP VALUE VOLATILE
NEW DPP VALUE NON-VOL ATILE
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. MD-2004 Rev. F
CAT522
READING DATA Each time data is transferred into a DPP control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DPP's output. This feature allows Ps to poll DPPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the non-volatile memory setting is reloaded into the DPP wiper control register. Since this value is the same as that which had been there previously no change in the DPP's output is noticed. Had the value held in the control register been different from that stored in nonvolatile memory then a change would occur at the read cycle's conclusion. TEMPORARILY CHANGE OUTPUT The CAT522 allows temporary changes in DPP's output to be made without disturbing the settings retained in non-volatile memory. This feature is parti- cularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. Figure 3 shows the control and data signals needed to effect a temporary output change. DPP wiper settings may be changed as many times as required and can be made to any of the two DPPs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all two DPPs will return to the output values stored in non-volatile memory. When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DPP wiper control register prior to programming. This is because the CAT522's internal control circuitry discards from the programming register the new data two clock cycles after receiving it if no PROG signal is received.
Figure 2. Reading from Memory
to 1 2 3 4 5 6 7 8 9 10 11 12
Figure 3. Temporary Change in Output
to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
CS
CS
NEW DPP DATA
DI 1 A0 A1
DI
CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 D6 D7
1
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 D6 D7
PROG
PROG
RDY/BSY
RDY/BSY
DPP OUTPUT
CURRENT DPP VALUE NON-VOL ATILE
DPP OUTPUT
CURRENT DPP VALUE NON-VOL ATILE
NEW DPP VALUE VOLATILE
CURRENT DPP VALUE NON-VOL ATILE
Doc. No. MD-2004 Rev. F
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(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT522
APPLICATION CIRCUITS
+5V VI RI +15V RF
DPP INPUT DPP OUTPUT VDPP = MSB LSB CODE V - VZERO + VZERO 255 FS ANALOG OUTPUT
VFS = 0.99VREF
VREF = 5V
RI = RF
GND
VREFL VOUT =
VDPP ( RI + RF ) - VI R F RI
For R I = RF VOUT = 2VDPP - VI
+5V
RI +15V
GND
VREFL
R VOUT = (1 + F ) VDPP RI
Amplified DPP Output
VDD CONTROL & DATA
CAT522
GND VREFL
Digitally Controlled Voltage Reference
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
+
CONTROL & DATA
CAT522
-
VDD
VREFH
-15V
VREFH
+
-15V
CONTROL & DATA
CAT522
-
OP 07
VDD
VREFH
VOUT
1111 1000 0111 0000 0000 1111 0000 1111 0001 0000
VZERO = 0.01VREF
255 x 0.98VREF + 0.01VREF = 0.990VREF 255 128 x 0.98VREF + 0.01VREF = 0.502VREF 255 127 x 0.98VREF + 0.01VREF = 0.498 VREF 255 1 x 0.98VREF + 0.01VREF = 0.014 VREF 255 0 x 0.98VREF + 0.01VREF = 0.010 VREF 255
VOUT = +4.90V VOUT = +0.02V
VOUT = -0.02V
VOUT = -4.86V VOUT = -4.90V
Bipolar DPP Output
V+ I > 2mA
RF
VOUT OP 07
VREF = 5.00V VDD
CONTROL & DATA
VREFH
LT 1029
CAT522
GND
VREFL
Digitally Trimmed Voltage Reference
28 - 32V
15k
10F
1N5231B 5.1V
10k
+
MPT3055EL
-
LM 324 OUTPUT 4.02k
1.00k
10F 35V
0 - 25V @ 1A
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Doc. No. MD-2004 Rev. F
CAT522
+5V VDD VREF VREFH 127RC
+5V VDD
+VREF VREFH 127RC RC = RC
R0 = (+VREF) - (VOFFSET+)
1A
FINE ADJUST DPP
FINE ADJUST DPP
CAT522
COARSE ADJUST DPP
GND
CAT522
RC VOFFSET +V
(-VREF) + (VOFFSET+)
1A
+ -
COARSE ADJUST DPP
GND
VREFL
VREFL -VREF
R0
VOFFSET
+V
+ -
-V
RC =
VREF
256 x 1A
Fine adjust gives 1 LSB change in VOFFSET when VOFFSET = VREF/2
Coarse-Fine Offset Control by Averaging DPP Outputs for Single Power Supply Systems
+5V 2.2k VDD VREFH 4.7F
Coarse-Fine Offset Control by Averaging DPP Outputs for Dual Power Supply Systems
LM385-2.5 +15V
ISINK = 2 - 255mA
DPP1
+
+5V
-
10k 10k
2N7000
1mA steps
CONTROL & DATA
CAT522
39 1W
39 1W
DPP2
+ -
2N7000
5A steps
GND
VREFL
5M
5M
3.9k
10k
10k
Current Sink with 4 Decades of Resolution
Doc. No. MD-2004 Rev. F
10
+
-15V
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
-
TIP30
CAT522
+15V 51k
+
TIP29
-
10k +5V
10k
VDD
VREFH
5M DPP1
5M
39 1W 39 1W
5M DPP2
GND
VREFL
LM385-2.5 -15V ISOURCE = 2 / 255mA
Current Source with 4 Decades of Resolution
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
11
+
5M 3.9k
CONTROL & DATA
CAT522
+
-
BS170P 1mA steps
-
BS170P 5A steps
Doc. No. MD-2004 Rev. F
CAT522
PACKAGE OUTLINE DRAWING PDIP 14-Lead (L) (1)(2)
SYMBOL MIN NOM MAX
A A1 A2
E1
3.56 0.38 2.92 0.36 1.15 0.21 18.67 7.62 6.10 7.88 2.99 3.30 3.30 0.45 1.52 0.26 19.05 7.87 6.35 2.54 BSC
5.33 4.95 0.55 1.77 0.35 19.68 8.25 7.11 10.92 3.81
b b1 c D E E1 e eB L
D
TOP VIEW
E
A2
A c
A1
L
e
b1
b
eB
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-001.
Doc. No. MD-2004 Rev. F
12
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT522
SOIC 14-Lead (W) (1)(2)
SYMBOL
MIN
NOM
MAX
A A1 b c
E1 E
1.35 0.10 0.33 0.19 8.55 5.80 3.80 0.25 0.40 0 8.65 6.00 3.90 1.27 BSC
1.75 0.25 0.51 0.25 8.75 6.20 4.00 0.50 1.27 8
D E E1 e h L
PIN#1 IDENTIFICATION
TOP VIEW
D
h
A
e
b A1
L
c
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012.
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. MD-2004 Rev. F
CAT522
EXAMPLE OF ORDERING INFORMATION
Prefix
CAT
Optional Company ID
Device # Suffix
522 W I
Temperature Range I = Industrial (-40C to 85C)
-
T2
Tape & Reel T: Tape & Reel 2: 2000/Reel
Product Number 522
Package L: PDIP W: SOIC
Notes: (1) (2) (3) All packages are RoHS compliant (Lead-free, Halogen-free). Standard lead finish is Matte-Tin. This device used in the above example is a CAT522WI-T2 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel)
ORDERING PART NUMBER
CAT522LI CAT522WI
Doc. No. MD-2004 Rev. F
14
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
REVISION HISTORY Date 3/16/2004 7/12/2004 Rev. D E Reason Updated Potentiometer Characteristics Updated Functional Diagram Updated Potentiometer Characteristics Add Package Outline Drawings Update Example of Ordering Information Updated Ordering Information Added MD- to document number
07/26/2007
F
Copyrights, Trademarks and Patents (c) Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Beyond MemoryTM, DPPTM, EZDimTM, LDDTM, MiniPotTM, and Quad-ModeTM Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com
Document No: MD-2004 Revision: F Issue date: 07/26/07

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